This invention generally relates to transconductance amplifiers, that is amplifiers which produce an output current in response to an input voltage, and to analogue-to-digital converters (ADCs) employing such amplifiers. More particularly the invention relates to transconductance amplifiers in which an output current depends upon the difference between two input voltages, and to their applications.
In many ADC designs an analogue input voltage is compared to a reference voltage (or a plurality of reference voltages) to produce a voltage output which can be used to generate a digital output code. Exemplary voltage comparators are described in U.S. Pat. No. 6,150,851, U.S. Pat. No. 6,356,148, U.S. Pat. No. 6,249,181 and D. R. Beck and D. J. Allstot, xe2x80x9cAn 8-bit, 1.8V, High Speed Analogue-to-Digital Converterxe2x80x9d (http://students.washington.edu/beckdo/papers/techcon2000.doc) and P. Setty, J. Barner, J. Plany, H. Burger and J. Sonntag, xe2x80x9cA 5.75b 350MSamples/S or 6.75b 150MSamples/S reconfigurable/ADC for a PRML Read Channelxe2x80x9d, Session 9 IEEE International Solid-State Circuit Conference 5-7 February 1998 (ISSCC98). Sample and Hold (S/H) circuits for ADCs are also known, such as those described in U.S. Pat. No. 6,169,427 and U.S. Pat. No. 5,963,156 and N. Waltari and K. Halonen, xe2x80x9c1.0-Volt, 9-bit Pipeline CMOS ADCxe2x80x9d, 26th European Solid-State Circuit Conference Stockholm, Sweden 19-21 September 2002 which all use a conventional (voltage output) operational amplifier with switched capacitor feedback. Also known are Successive-Approximation-Register (SAR) analogue-to-digital converters (see, for example, J. L. McCreary and P. Gray, IEEE JSSC SC-10 pp371-9, Dec 1975) which compare an analogue input with the output of a digital-to-analogue converter (DAC), which DAC may employ a binary-weighted capacitor array to generate an analogue output voltage using charge redistribution between the capacitors.
The above-mentioned analogue-to-digital converters use voltage comparisons to generate a digital output. It will be appreciated that when comparing an input voltage to a reference voltage only gain, and not linearity is important since it is merely necessary to know whether the input is above or below the reference. However it is also known to simplify ADC circuits by summing currents generated by interpolating between reference voltages, and for this interpolation-type summing linearity is an important requirement. Interpolating ADCs are often used for low-resolution high-or medium-speed applications. FIG. 1 shows a generalised circuit diagram of an exemplary stage of a current-mode interpolating ADC. Examples of ADCs with current-mode interpolation are described in M. P. Flynn and D. J. Alstot, xe2x80x9cCMOS Folding A/D Converters with Current-Mode Interpolationxe2x80x9d, IEEE JSSC, vol. 31, September 1996 pages 1248-1257; M. P. Flynn and B. Sheahan, xe2x80x9cA 400MSample/S, 6-b CMOS Folding and Interpolating ADCxe2x80x9d IEEE JSSC, vol. 33, Dec. 1998, pages 1932-1938; B-S Song, P. L. Rakers and S. F. Gillig, xe2x80x9cA 1V, 6-b 50MSamples/S Current Interpolating CMOS ADCxe2x80x9d, IEEE J. Solid-State Circuits, vol. 35, April 2000, pages 647-651.
Referring to FIG. 1a, the general principle is to generate a plurality of comparison levels (five in FIG. 1) from a smaller set of reference voltages (two, VrefA and VrefB, in FIG. 1) by interpolating between the outputs from a set of amplifiers (two in FIG. 1), each of which outputs represents the difference between an input signal and one of the references.
In the interpolating stage 100 of FIG. 1a an input voltage on line 102 is provided to one input of first 104 and second 106 differential transconductance amplifiers. A second input to the first transconductance amplifier 104 is provided by a first reference voltage VrefA on line 108 and a second input to differential transconductance amplifier 106 is provided by a second reference voltage VrefB on line 110. Each differential transconductance amplifier generates an output current in proportion to the difference between the voltages on its two inputs, the ratio of output current to input voltage difference being termed the transconductance. Amplifiers 104 and 106 are drawn as current sinks but preferably their output currents can be of either positive or negative polarity according to the polarity of Vin-VrefA and Vin-VrefB respectively.
FIG. 1b illustrates one possible implementation of a transconductance amplifier 130 suitable for use for transconductance amplifiers 104 and 106. The transconductance amplifier comprises a pair of input transistors 132, 134 with inputs from, respectively, Vin 102 and one of VrefA 108 and VrefB 110, and a common source connection connected to a constant current sink 136. The drain connections of transistors 132 and 134 are connected to respective input and output connections of a current mirror enclosed by dashed line 138, and a current output connection 140 is taken from the junction of the drain of transistor 134 with the output of current mirror 138. Each of transistors 132, 134 passes an incremental current given by its transconductance gm, multiplied by the incremental gate input voltage of the transistor so that the output current is given by Iout=Gm.(Vinxe2x88x92Vref) where the transconductance, Gm, of the amplifier is equal to gm.
The output current from transconductance amplifier 104 is input to or drives a first current mirror 112 and the output current from transconductance amplifier 106 drives a second current mirror 114. Current mirror 112 comprises a plurality of constant current generators 112a-e. In a conventional manner, a voltage on line 116 sets the current through element 112a to be the same as the output current flowing into differential transconductance amplifier 104. This same drive voltage is also provided to elements 112b-e to provide constant current outputs on lines 118a-d determined by the output current of transconductance amplifier 104.
FIG. 1c shows an example of a controllable current generator 150 suitable for use in the interpolating ADC stage 100 of FIG. 1a. An input transistor 151 and a constant current sink 152 are connected in series between power supply lines 154, 156, a connection between transistor 151 and current sink 152 providing a current output Iout 158. Input transistor 151 has a control voltage Vc applied to its gate connection to provide a controlled, unipolar current equal to the sum of the output current Iout and the current through the constant current sink 152. Thus the output current may be of either polarity depending upon the magnitude of the controlled unipolar current through input transistor 151. For a given input control voltage Vc the output current (or the outputs of a plurality of matched controllable current generators) can be scaled by scaling the dimensions of input (MOS) transistor 151. The current sink 152 is preferably scaled in the same ratio to maintain a constant xe2x80x9czero currentxe2x80x9d point. In this way a plurality of differently-scaled, matched controllable current generators may be arranged to have zero output current for substantially the same input control voltage, and thus to provide zero output current substantially simultaneously.
Where transistors comprising elements 112a and 112b have the same physical size the current on line 118a is substantially the same as the current through element 112a. The sizes of transistors comprising elements 112c, d, e are reduced to 0.75xc3x97, 0.5xc3x97 and 0.25xc3x97that of element 112b so that respective currents of 0.75xc3x97, 0.5xc3x97 and 0.25xc3x97 the output current from transconductance amplifier 104 are provided on lines 118b, 118c and 118d. Generally current mirror 112 is fabricated on an integrated circuit so that the transistors comprising the current mirror are matched. Current mirror 114 likewise comprises elements 114a-e, for example bipolar or FET transistors, and operates in a corresponding manner to provide, respectively, currents of 1.0xc3x97, 0.75xc3x97, 0.5xc3x97, and 0.25xc3x97 the output current of transconductance amplifier 106 on lines 120a-d. 
The current 11 on line 118a is provided to a comparator 122a to generate a digital output D1. Digital output D2 from comparator 122b is determined by a sum of the currents on lines 118b and 120d; output D3 from comparator 122c is determined by a sum of currents on lines 118c and 120c; output D4 from comparator 122d is determined by a sum of currents on lines 118d and 120b and digital output D5 from comparator 122e is determined by the current in line 120a. Denoting the output current of transconductance amplifier 104 IA and the output current of transconductance amplifier 106 IB, IA is proportional to the difference between Vin on line 102 and VrefA on line 108 and IB is proportional to the difference between Vin and VrefB on line 110. The summed intermediate currents are proportional to a fraction of the difference between Vin and VrefA plus a fraction of the difference between Vin and VrefB. In mathematical terms:
I1=IA=G(Vinxe2x88x92VrefA) 
I5=IB=G(Vinxe2x88x92VrefA) 
I2=0.75 G(Vinxe2x88x92VrefA)+0.25G(Vinxe2x88x92VrefB) 
therefore
I2xe2x88x9dVinxe2x88x92(0.75 VrefA+0.25VrefB) 
and
I2xe2x88x9dVinxe2x88x92(3VrefA+VrefB)/4. 
In other words these scaled currents generate output currents proportional to the residues [Vinxe2x88x92Vth(i)] i=1 . . . 5 where:
Vth(1)=VrefA, 
Vth(2)=(3.VrefA+VrefB)/4, 
Vth(3)=(VrefA+VrefB)/2, 
Vth(4)=(VrefA+3.VrefB)/4, 
Vth(5)=VrefB. 
It can be seen that where Vin=Vth the output current is zero and that for Vin greater than Vth the output current is positive and for Vin less than Vth the output current is negative. Thus the output currents 11 to 15 will cross zero at input voltages equal to thresholds Vth(1), . . . , N where N=(2+no. of intermediate values), in this case 5 (i.e. 2+3). In the interpolating stage circuit 100 of FIG. 1 the output currents 11 to 15 are applied to high input impedance comparators 122a to 122e respectively which make logic decisions at these thresholds. Thus input voltage Vin signal levels between VrefA and VrefB are converted to a digital format output on lines D1 to D5 as a so-called thermometer code. This code is then converted to a binary code by conventional means (not shown in FIG. 1). This may comprise, for example, a priority encoder or alternatively the functionality of the hardware may be specified in a hardware description language such as Verilog (Trade Mark) or VHDL, allowing a hardware synthesis tool to blend in the code conversion functionality with other back-end logic such as error correction logic.
Although in FIG. 1 only two reference voltages, VrefA and VrefB, are illustrated more reference voltages may be employed for multiple (binary) bit conversion. The reference voltages are typically derived from a resistor string and the skilled person will appreciate that compared to a conventional/analogue-to-digital converter fewer taps on such a resistor string are necessary since fewer reference voltages are required. Furthermore the amplification of the residue signal also eases the requirements on the comparators, and in particular the requirements on their omitted input offset voltage and overdrive. Typically this saves the need for a preamplification stage before each comparator, so that the overall circuit is simpler despite the added current mirrors and linear transconductance amplifiers.
One application of an interpolating ADC is as the second stage of a two-stage analogue-to-digital converter such as, the analogue-to-digital converter 200 shown in FIG. 2. In this ADC an input voltage Vin on line 202 is provided to an M-bit ADC 204 which outputs the M most significant bits (MSBs) of the digitised signal on line 206. This coarse approximation to the input voltage Vin is converted back to an analogue voltage by an M-bit digital-to-analogue converter 208 and subtracted from the original input signal by subtractor 210 to leave a residual signal on line 212. This residual signal is presented to an N-bit analogue-to-digital converter 214 which generates the N least significant bits (LSBs) on line 216 which are combined with the MSBs by suitable logic in combiner 218 to provide a digital output 220 with the required total number of binary bits. An example of such a two-stage ADC is described in xe2x80x9cA 3.3-V, 10-b, 25-MSample/s Two-Step ADC in 0.35-xcexcm CMOSxe2x80x9d, Hendrik van der Ploeg and Robert Remmers, IEEE Journal of Solid State Circuits, Vol 34, No 12, December 1999. The coarse and fine stage conversions ranges may be overlapped to ease constraints on the coarse stage ADC.
It can be seen by inspection of FIG. 2 that the first stage ADC 204 must first make its decision and then the output of DAC 208 and of the difference amplifier 210 must settle before second stage comparators associated with ADC 214 make their decision. Thus the first stage must sample its input signal well before the second stage decision time. To avoid conversion errors it has previously been necessary to precede such a two-stage ADC with a sample-and-hold circuit to hold the input constant between the two sampling instants. This increases the complexity of the ADC, thus increasing its cost, and also increases the power consumption. It is therefore desirable to be able to dispense with such a sample-and-hold circuit, particularly whilst retaining the linearity desirable for interpolation-type summing and other linear signal processing.
According to a first aspect of the present invention there is therefore provided a difference amplifier configured for providing an output current dependent upon a difference between a first input voltage and a second input voltage, the difference amplifier comprising an input sampling capacitor having two conductors; a transconductance amplifier having an input coupled to a first conductor of said input sampling capacitor and a current output suitable for generating said output current; and an input switch for selectively coupling a second conductor of said input sampling capacitor to a first input of said difference amplifier for receiving said first input voltage and to a second input of said difference amplifier for receiving said second input voltage; the difference amplifier being configured to, in a first state, couple said second conductor to one of said first and second inputs and apply a voltage to said first conductor and to, in a second state, couple said second conductor to the other of said first and second inputs to provide a voltage change to said transconductance amplifier input dependent upon said difference between said first and second input voltages.
Preferably, the output current is substantially linearly dependent upon the difference between the first and second input voltages. The output current may be provided directly from the transconductance amplifier or the current generated by the transconductance amplifier may be mirrored or used in some other way to provide an output current for said difference amplifier.
The input sampling capacitor allows one input voltage, say the first, to be sampled in the difference amplifier""s first state, to set a charge on the input sampling capacitor. Then, when the second conductor of the input sampling capacitor is connected to the other input voltage, say the second, the voltage difference between the inputs is transferred to the input of the transconductance amplifier which provides a current output for generating, either directly or indirectly, the output current from the difference amplifier. A controller may be employed to control this sampling process. Provided that the transconductance amplifier is itself linear the difference amplifier is also substantially linear.
In operation the first voltage is sampled onto the input capacitor at the end of the first state, but its value is held and subtracted from the second voltage during the second state. The output current resulting from the difference voltage may be sampled (by a following comparator) at the end of the second state, giving the second voltage additional time to settle. This sample and hold action is particularly useful for two-stage ADCs, where the first voltage can be the original input signal, and the second voltage is a reference voltage chosen by a xe2x80x9ccoarsexe2x80x9d ADC also sampling the input signal. Since the second, reference voltage is not needed until the start of the second state the xe2x80x9ccoarsexe2x80x9d ADC has time to settle, and the need for a separate sample-hold circuit can be avoided.
In a refinement of the difference amplifier one or more additional input sampling capacitors may be provided. Such an additional input sampling capacitor may be switched between two reference voltages and where a plurality of difference amplifiers is employed, for example in an two-stage ADC, one of these reference voltages may be common to all the difference amplifiers and the other reference voltage applied to each difference amplifier may be tied to respective points in a ladder of reference voltages.
In this way the effective operating points of the difference amplifiers may be spaced apart, for example substantially equidistantly, to provide two or more output currents which may be summed for use by an interpolating ADC. Each difference amplifier may be arranged to generate multiple scaled output currents, for example for use in current-mode interpolation.
It will be recognized that the first conductor of the input sampling capacitor need not be connected to the transconductance amplifier input in the difference amplifier""s first state and it could, for example, be coupled to the input of the transconductance amplifier via a switch. However in a preferred embodiment the voltage applied to the first conductor in the first state of the difference amplifier is a virtual earth voltage, that is for a differential transconductance amplifier a voltage on one of the inputs is maintained by a closed feedback path to be substantially the same as a (preferably fixed) voltage on the other differential input. This can be provided by means of a switched DC feedback path, either from the output of the transconductance amplifier or from a later stage in the difference amplifier such as after an output drive device, for example a device providing a mirrored or split output current. In a preferred embodiment a positive differential input of the transconductance amplifier is connected to a fixed reference voltage such as ground and a negative differential input of the transconductance amplifier is connected to the input sampling capacitor. Preferably a low resistance switch such as an FET switch is then provided to couple the negative differential input to a current output of the difference amplifier. This virtual earth connection allows the input offset voltage of the transconductance amplifier to be cancelled.
The voltage change provided to the transconductance amplifier input in changing from the first to the second state of the difference amplifier may be substantially equal to the difference between the first and second input voltages, for example where there is only a single input sampling capacitor or the voltage change may be scaled, for example where there is some charge sharing between two or more input sampling capacitors.
A differential difference amplifier may be constructed along similar lines, using a pair of the above-described difference amplifiers, but using a shared, differential transconductance amplifier so that, in effect, one input switch and one set of first and second input voltages is associated with each differential input (positive and negative) of the differential transconductance amplifier. In this way, the differential difference amplifier is responsive to a differential signal comprising two sets of voltage differences between two sets of said first and second input voltages. Generally speaking, one set of first input voltages will comprise a positive and negative first input voltage and one set of second input voltages will comprise a positive and negative second input voltage. The circuit may similarly be extended, as described above, by providing one or more additional sets of (differential) input sampling capacitors and/or by adding further (differential) transconductance amplifiers and/or by mirroring or otherwise providing a plurality of single-ended or differential outputs.
Thus in a related aspect the invention also provides a differential difference amplifier for providing an output current dependent upon a differential signal at a differential input comprising two pairs of signal inputs, said differential signal comprising two voltage differences, a first being dependent upon a difference between first and second input voltages on a first pair of said pairs of signal inputs, a second being dependent upon a difference between third and fourth input voltages on a second pair of said pairs of signal inputs, said differential difference amplifier comprising: first and second input sampling capacitors, each having two conductors, for said first and second pair of signal inputs respectively; a differential transconductance amplifier having a differential input coupled to said first and second input sampling capacitors and an output for generating said output current; a pair of input switches, one for each of said pair of signal inputs, for selectively coupling said first and second input sampling capacitors respectively to one of said first and second input voltages and to one of said third and fourth input voltages; a pair of initialisation switches to bring plates of said first and second input sampling capacitors coupled to said differential transconductance amplifier to initial voltages; and a controller to control said input switches and said initialisation switches to apply said differential signal to said differential transconductance amplifier.
The plates of the sampling capacitors may be brought to the same initial voltage or to different initial voltages, the output current may either comprise a single-ended or a differential output current and, again, the circuit may be extended by providing additional pairs of sampling capacitors for additional differential inputs, each additional pair of sampling capacitors having an associated pair of input switches for determining a pair of input voltage differences.
According to another aspect of the present invention there is provided an analogue-to-digital converter comprising at least one transconductance amplifier configured to provide a plurality of output currents at a plurality of outputs; and a plurality of comparators coupled to said plurality of transconductance amplifier outputs for providing a digital output; at least one switched input sampling capacitor coupled to an input of said transconductance amplifier; and at least one switch configured to couple said input sampling capacitor alternately to a first reference voltage and to an analogue voltage for conversion.
The analogue-to-digital converter may comprise, for example, a current-mode interpolating or folding converter, preferably comprising a plurality of stages. As previously described, by providing an input sampling capacitor and a switch to alternately couple the capacitor to an analogue voltage for conversion and to a reference voltage a sampling difference amplifier is provided which, in embodiments enables a prior sample-hold to be dispensed with. In embodiments a pair of input sampling capacitors may be provided for each of a plurality of transconductance amplifiers, to allow for combinations of output currents with zero crossings at regularly spaced input voltage thresholds, thereby creating a ladder of zero crossing threshold voltages for use in generating the digital output. In embodiments the digital output comprises a thermometer code which is converted to a binary representation.
The analogue-to-digital converter may be used as the second stage in a two-stage analogue-to-digital converter in which a first analogue-to-digital converter provides a digital output to a first number of (most significant) bits accuracy to provide a coarse approximation to an analogue input signal. This coarse approximation may then be used as the reference voltage for the input sampling capacitor for generating one or more least significant output bits of the two-stage analogue-to-digital converter.
According to a related aspect of the invention there is provided a method of generating a current in substantially linear dependence upon a voltage difference between first and second voltages using a circuit comprising a switch, a switched input capacitor, and a substantially linear transconductance amplifier, a first plate of the input capacitor being coupled to an input of the transconductance amplifier, a second plate of the input capacitor being switchably couplable to the first and second voltages, the method comprising coupling the second plate of the input capacitor to the first voltage whilst maintaining the first plate at a reference voltage to charge the input capacitor; and then coupling the second plate of the input capacitor to the second voltage and allowing the potential of the first plate to change by an amount dependent upon said voltage difference to cause said transconductance amplifier to generate an output current substantially linearly dependent upon said voltage difference.
When the input capacitor is connected to the first voltage and to the reference voltage it is charged, that is it is brought to a defined state of charge by charge flowing onto or off the capacitor. Then by connecting the second plate of the input capacitor to the second voltage the difference between the first and second voltages is substantially transferred to the input of the transconductance amplifier.
In another aspect the invention provides a method of generating a current substantially linearly dependent upon two voltage differences, a first voltage difference between first and second voltages and a second voltage difference between third and fourth voltages, the method employing a circuit comprising first and second switches, first and second switched input capacitors, and a substantially linear transconductance amplifier, a first plate of the first input capacitor and a first plate of the second input capacitor being coupled together and coupled to an input of the transconductance amplifier, a second plate of the first input capacitor being coupled to the first switch for switchable coupling to the first and second voltages and a second plate of the second input capacitor being coupled to the second switch for switchable coupling to the third and fourth voltages, the method comprising coupling the second plates of the first and second input capacitors to the first and third voltages respectively whilst maintaining the first plates of the capacitors at a reference voltage, to charge the input capacitors; and then coupling the second plates of the first and second input capacitors to the second and fourth voltages respectively and allowing the charge on the first plates of the capacitors to be shared such that the potential of the first plates changes by an amount dependent upon both said first and second voltage differences to cause said transconductance amplifier to generate output current substantially linearly dependent upon both said voltage differences.
The input capacitors may be of different sizes or values, thus providing proportionate scaling of the respective input voltages.
There is also provided a difference amplifier configured to operate in accordance with these methods.
In a further aspect the invention provides a method of operating a two-stage analogue-to-digital converter, the two-stage analogue-to-digital converter comprising a first analogue to digital converter to provide a coarse approximation to an analogue input signal and a second analogue-to-digital converter comprising at least one difference amplifier configured for providing an output current dependent upon a difference between a first input voltage and a second input voltage, the difference amplifier comprising a transconductance amplifier for providing said output current for a comparator for providing a digital output, at least one switched input sampling capacitor coupled to an input of said transconductance amplifier, and at least one switch configured to couple said input sampling capacitor alternately to said first and second input voltages, the method comprising controlling said switch to couple said input sampling capacitor first to an analogue voltage for conversion and then to said coarse input signal approximation to provide a reference voltage.
Preferably the difference amplifier output current is substantially linearly dependent upon the difference between the first and second input voltages. More preferably the method comprises using a plurality of difference amplifiers for comparing the coarse input signal approximation with a plurality of reference levels, preferably by offsetting the reference levels of the difference amplifiers using a second switched input sampling capacitor for each amplifier.
The invention also provides an analogue-to-digital converter configured to operate in accordance with this method.